Semiconductor industry has made significant efforts in reducing feature sizes in digital circuits. As observed by Gordon Moore, transistor densities in high-density integrated circuits have doubled at a fairly steady rate (and this observation is often called “Moore's law”). For example, integrated circuits made in mid-1990s have feature sizes of approximately 350 nm, whereas integrated circuits made in 2014 have feature sizes approaching 14 nm. Such reduction of feature sizes has allowed cost reduction, as more chips can be made using a single die of a silicon wafer.
However, reducing feature sizes has introduced additional challenges. For example, the proximity between two adjacent wires has led to increased noise injection such as cross-talks. In addition, increased resistance and capacitance in wires have deteriorated delays in digital circuits.
Conventional methods for calculating delays, noise injections, and power consumptions on a single computer with a handful of processors are slow and inefficient for use with complex circuits, such as an application specific integrated circuit (ASIC) that includes multi-million logical gates.